//
//
//       DCS Decoder Block Version 1.00 for FPGA/ASIC targets
//       Adrian Tang 2016
//
//      You need to clock at twice the spreading-chip rate (IE 7.5 MS/s)
//      Verilog 2001
//
//      Typically a good PN code will be same number of 1s and 0s for minimal DC
//
//     Usage
//
//     1. Reset the block. 
//     2. As PN_codes are recgonized the bits they represent will be added to the output buffer
//     3. number_of_bits holds the current index of the output buffer
//        bits from output_buffer[0] to output_buffer[number_of_bits-1] are valid
//     4. The actual command decoder block (not implemented) should look at output buffer and when it recgonizes the packet
//        reset this block to prepare for capturing the next DCS packet
//
module DCS_decoder(reset, clk, dsss_stream, confidence_threshold, PN_code, number_of_bits, output_buffer);


//Main Block Control
input clk;     //mater clock on the block (7.5 MS/s)
input reset;   //master reset for the block tripped after each packet
reg sequencer;

//Block Inputs
input dsss_stream;                 //dsss stream from track
input [30:0] PN_code;              //Fixed PN Code input
input [7:0] confidence_threshold;  //Confidence Threshold Level

//Block Outputs
output [7:0] number_of_bits;    //Counts the number of bits detected
reg    [7:0] number_of_bits;
output [255:0] output_buffer;   //Actual output data
reg    [255:0] output_buffer; 

//Internal registers
reg [61:0]  sr_reg;     //Input shift register packet streams into
reg [30:0] eve_reg;     //Even phase subregister for decoder
reg [30:0] odd_reg;     //Odd phase subregister for decoder

//intermediate correlation values
reg [30:0] CE;  //even phase correlation
reg [30:0] CO;  //odd phase correlation
reg  [7:0] CE_TOTAL; //Accumulated even confidence
reg  [7:0] CO_TOTAL; //Accumulated even confidence


//Confidence Intervals for dsss
wire [7:0] con_high; 
wire [7:0] con_low;




//---------------Generate the tow level confidence levels------------------------------
assign con_high = confidence_threshold;            //we need more than (confidence_threshold) out of 31 spread chips to match to take it as 1
assign con_low  = 7'd31 - confidence_threshold;     //we need more than (confidence_threshold) out of 31 spread chips NOT to match to take it as 0


//----decoder core operation begins here

always@ (posedge clk)
begin //always on clock synchronous ooperation

//------------------------------------------------------------------------------------------------------------------------------------------------------------------------
//                                                              MAIN CORRELATOR
//------------------------------------------------------------------------------------------------------------------------------------------------------------------------


//input 62 bit shift register to take in the track data
sr_reg <= sr_reg >> 1; 
sr_reg[61] <= dsss_stream; 

//-----------------Assign the odd and even registers from the main shift register in order to cover both possible phases----------------
odd_reg <= {sr_reg[60],sr_reg[58],sr_reg[56],sr_reg[54],sr_reg[52],sr_reg[50],
                   sr_reg[48],sr_reg[46],sr_reg[44],sr_reg[42],sr_reg[40],sr_reg[38],
                   sr_reg[36],sr_reg[34],sr_reg[32],sr_reg[30],sr_reg[28],sr_reg[26],
                   sr_reg[24],sr_reg[22],sr_reg[20],sr_reg[18],sr_reg[16],sr_reg[14],
                   sr_reg[12],sr_reg[10],sr_reg[8], sr_reg[6], sr_reg[4], sr_reg[2],
                   sr_reg[0]};
                  
                  
eve_reg <= {sr_reg[61],sr_reg[59],sr_reg[57],sr_reg[55],sr_reg[53],sr_reg[51],
                  sr_reg[49],sr_reg[47],sr_reg[45],sr_reg[43],sr_reg[41],sr_reg[39],
                  sr_reg[37],sr_reg[35],sr_reg[33],sr_reg[31],sr_reg[29],sr_reg[27],
                  sr_reg[25],sr_reg[23],sr_reg[21],sr_reg[19],sr_reg[17],sr_reg[15],
                  sr_reg[13],sr_reg[11],sr_reg[9], sr_reg[7], sr_reg[5], sr_reg[3],
                  sr_reg[1]};                 


//-------------Generate the 4 correlation terms--------------
//Even Phase Positive
CE <= eve_reg ~^ PN_code;
//Odd Phase Positive
CO <= odd_reg ~^ PN_code;


//-------------Compute the total correlation--------------
CE_TOTAL = CE[30] + CE[29] + CE[28] + CE[27] + CE[26] + CE[25] + CE[24] + CE[23] + CE[22] + CE[21] + 
           CE[20] + CE[19] + CE[18] + CE[17] + CE[16] + CE[15] + CE[14] + CE[13] + CE[12] + CE[11] + 
           CE[10] + CE[9]  + CE[8]  + CE[7]  + CE[6]  + CE[5]  + CE[4]  + CE[3]  + CE[2]  + CE[1] + 
           CE[0];

CO_TOTAL = CO[30] + CO[29] + CO[28] + CO[27] + CO[26] + CO[25] + CO[24] + CO[23] + CO[22] + CO[21] + 
           CO[20] + CO[19] + CO[18] + CO[17] + CO[16] + CO[15] + CO[14] + CO[13] + CO[12] + CO[11] + 
           CO[10] + CO[9]  + CO[8]  + CO[7]  + CO[6]  + CO[5]  + CO[4]  + CO[3]  + CO[2]  + CO[1] + 
           CO[0];


if(reset==1)
   //if the block is in reset mode
   begin
   number_of_bits<=8'd0;    //reset the bit counter
   output_buffer<=256'd0;   //Clear the output buffer
   sequencer<=1'b0;
   end
else
   //if the block is running
   begin

   sequencer <= ~sequencer;    //This ones a bit complicated. Ideally we have two samples per spreading chip but we don't want to double count
   if(sequencer==1)            //as the chip moves from the even side to the odd side, so we only look at both even and odd every 2 clocks
                               //to prevent double counting the same PN_code
   begin
   //-------------Decode to the output packet buffer--------------

       //If we have a "1" PN_code detected
       if ((CE_TOTAL > con_high) || (CO_TOTAL > con_high))
       begin
       number_of_bits <= number_of_bits + 8'd1; //increment the bit counter
       output_buffer[number_of_bits] = 1'b1;    //Set the output buffer to a 1 if we detected a 1
       end


      //If we have a "0" PN_code detected
      if ((CE_TOTAL < con_low) || (CO_TOTAL < con_low))      
      begin
      number_of_bits <= number_of_bits + 8'd1; //increment the bit counter
      output_buffer[number_of_bits] = 1'b0;    //Set the output buffer to a 1 if we detected a 1
      end 


      end //sequencer
   end  //reset =0 condition


end //on clock




endmodule