// // // DCS Tramitter Block Version 2.00 for FPGA/ASIC targets // Adrian Tang 2017 // // You need to clock at exactly the spreading-chip rate (IE 3.75 MS/s) // Verilog 2001 // // Typically a good PN code will be same number of 1s and 0s for minimal DC // // Usage // // 1. Reset the block. // 2. As PN_codes are recgonized the bits they represent will be added to the output buffer // 3. number_of_bits holds the current index of the output buffer // bits from output_buffer[0] to output_buffer[number_of_bits-1] are valid // 4. They will be streamed out the USART module DCS_spoof(reset, clk, track_stream, done); //----------------------------------------------------------------------------------------------------------------- // MTH SPREAD CODE SECTION //----------------------------------------------------------------------------------------------------------------- //MTH code flipped for reference: 1011101000001001100011110010101 //MTH code inverte for reference: 0100010111110110011100001101010 parameter PN_code = 31'b1010100111100011001000001011101; //MTH Secret Spread Code //----------------------------------------------------------------------------------------------------------------- // COMMAND SECTION //----------------------------------------------------------------------------------------------------------------- //THIS IS THE DCS CODE WE WISH TO SEND // THE DCS FORMAT GOES LIKE THIS // 11111111111111 // 0 // (Engine # 49 in this example) // 1 // some command // 111111111111111111 //Props to SanDiegoMark for helping me figure this out ... he's really really good at this! //whistle code 11111111 11111110 01001100 10100000 00000000 01000000 01100011 11111111 parameter command_length = 8'd63; parameter command = 64'b1111111111111110010011001010000000000000010000000110001111111111; //whistle command? //parameter command = 64'b1111111111111110010011001001000000000000000000000010001111111111; //coupler command? //Main Block Control input clk; //mater clock on the block (3.75 MS/s) input reset; //master reset for the block tripped after each packet //Block Output output track_stream; //dsss stream from track reg track_stream; output done; reg done; //---------------------------Internal Counters------------------------------------------------ reg [5:0] spread_counter; //Counts where we are in the spread code reg [7:0] bit_counter; //Counts where we are in the command //------------------------------------------------------------------------------------------------------------------------------------------------------------------------ // MAIN CORRELATOR //------------------------------------------------------------------------------------------------------------------------------------------------------------------------ always@ (posedge clk) begin //always on clock synchronous ooperation if(reset==0) begin //if the block is in reset mode spread_counter<=6'd0; //reset the spread counter bit_counter<=command_length; //Clear the output buffer done <= 1'b0; end //reset=0 condition else begin if(done==1'b0) begin //increment the spread chip counter every clock spread_counter<=spread_counter+6'd1; //check to see which spread-chip we're on //invert it if the current byte is 0 case(spread_counter) 6'd0: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[0]; end else begin track_stream<=~PN_code[0]; end end 6'd1: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[1]; end else begin track_stream<=~PN_code[1]; end end 6'd2: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[2]; end else begin track_stream<=~PN_code[2]; end end 6'd3: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[3]; end else begin track_stream<=~PN_code[3]; end end 6'd4: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[4]; end else begin track_stream<=~PN_code[4]; end end 6'd5: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[5]; end else begin track_stream<=~PN_code[5]; end end 6'd6: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[6]; end else begin track_stream<=~PN_code[6]; end end 6'd7: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[7]; end else begin track_stream<=~PN_code[7]; end end 6'd8: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[8]; end else begin track_stream<=~PN_code[8]; end end 6'd9: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[9]; end else begin track_stream<=~PN_code[9]; end end 6'd10: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[10]; end else begin track_stream<=~PN_code[10]; end end 6'd11: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[11]; end else begin track_stream<=~PN_code[11]; end end 6'd12: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[12]; end else begin track_stream<=~PN_code[12]; end end 6'd13: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[13]; end else begin track_stream<=~PN_code[13]; end end 6'd14: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[14]; end else begin track_stream<=~PN_code[14]; end end 6'd15: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[15]; end else begin track_stream<=~PN_code[15]; end end 6'd16: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[16]; end else begin track_stream<=~PN_code[16]; end end 6'd17: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[17]; end else begin track_stream<=~PN_code[17]; end end 6'd18: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[18]; end else begin track_stream<=~PN_code[18]; end end 6'd19: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[19]; end else begin track_stream<=~PN_code[19]; end end 6'd20: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[20]; end else begin track_stream<=~PN_code[20]; end end 6'd21: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[21]; end else begin track_stream<=~PN_code[21]; end end 6'd22: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[22]; end else begin track_stream<=~PN_code[22]; end end 6'd23: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[23]; end else begin track_stream<=~PN_code[23]; end end 6'd24: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[24]; end else begin track_stream<=~PN_code[24]; end end 6'd25: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[25]; end else begin track_stream<=~PN_code[25]; end end 6'd26: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[26]; end else begin track_stream<=~PN_code[26]; end end 6'd27: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[27]; end else begin track_stream<=~PN_code[27]; end end 6'd28: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[28]; end else begin track_stream<=~PN_code[28]; end end 6'd29: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[29]; end else begin track_stream<=~PN_code[29]; end end 6'd30: begin if (command[bit_counter] == 1'b1) begin track_stream<=PN_code[30]; end else begin track_stream<=~PN_code[30]; end end 6'd31: begin bit_counter<=bit_counter-8'd1; spread_counter<=6'b0; if (bit_counter == 8'd0) begin done <=1'b1; track_stream<=0; end end endcase end //done =0 condition end //reset =1 condition end //on clock endmodule