//
//
//       Epically Simple UART Transmitter for FPGA/ASIC targets
//       Adrian Tang 2017
//
//      You need to clock at 7.5 MS to get 9600 baud
//      
//     Verilog 2001
//
//     Usage
//
//     1. reset = 0
//     2. Apply tx_byte
//     3. reset = 1
//     4. data is sent
//     5. send_done goes high when finished

//module UART(reset, clk, tx_byte, TXD, send_done, baud_clock);
module UART(reset, clk, TXD, tx_byte, send_done, baud_clock);


//This parameter sets the division ratio to achieve the correct bit time for the RS232 signal
parameter baud_count = 13'd126;




//Main Block Control
input clk;       //mater clock on the block (7.5 MS/s)
input reset;     //master reset to singal the start of each byte transmitted

//data input
input [7:0] tx_byte;   //byte to be transmitted

//data output
output TXD;              //output transmit signal
reg TXD;

output send_done;        //output led indicating transmission is done
reg send_done;


//internal registers
reg [4:0]  packet_counter;     //counts the position in the packet
reg [12:0]  baud_counter;      //counts the baud division factor 


//clock generation relat
output baud_clock;            //output to monitor the baud clock rate
reg baud_clock;


always@ (posedge clk)
begin //always on clock synchronous operation
if(reset == 0)
   begin //RESET all the conditions
   baud_counter <=12'd0;
   baud_clock<=1'b0;
   send_done <=1'b0;
   packet_counter<=5'd0;   
   TXD<=1'b1;
   end  //reset=0

//UART CORE IS RUNNING
if(reset == 1)
   begin
      //CHECK THE BAUD DIVIDDER
      if(baud_counter<baud_count)   //IF WE HAVENT ACHIEVED THE BAUD COUNT KEEP COUNTING
            begin
            baud_counter<=baud_counter +13'd1;
            end
      else
            begin    //IF THE BAUD COUNT IS ACHIEVED
            baud_counter<=13'd0;       //RESET THE BAUD COUNT
            baud_clock <=~baud_clock;  //FLIP THE BAUD CLOCK                                      
            if(packet_counter < 5'd15)  //If the packet counter is not done
                begin
                packet_counter=packet_counter+5'd1;   //increment the counter
                                                      //send the packet
                    case (packet_counter)
                    5'd0:   TXD<=1'b1; //IDLE
                    5'd1:   TXD<=1'b0; //START BIT
                    5'd2:   TXD<=tx_byte[0]; //D0
                    5'd3:   TXD<=tx_byte[1]; //D1
                    5'd4:   TXD<=tx_byte[2]; //D2
                    5'd5:   TXD<=tx_byte[3]; //D3
                    5'd6:   TXD<=tx_byte[4]; //D4
                    5'd7:   TXD<=tx_byte[5]; //D5 
                    5'd8:   TXD<=tx_byte[6]; //D6
                    5'd9:   TXD<=tx_byte[7]; //D7
                    5'd10:  TXD<=1'b1; //STOP BIT
                    5'd11:  TXD<=1'b1; //IDLE
                    5'd12:  TXD<=1'b1; //IDLE            
                    5'd13:  TXD<=1'b1; //IDLE
                    5'd14:  send_done<=1'b1; //INDICATE THAT WE'RE DONE
                    endcase
               end //packet<15                                             
               end  //baud count                                   
       end  //reset=1
end //always on clock
endmodule