Skip to main content

Reply to "Semaphore and 555 Timer Circuit"

The 4017 has a so-called "active high" reset which means you briefly apply a positive supply voltage level signal.  That's what GRJ's suggestion does.  When you initially apply power the capacitor is discharged so there's no voltage across it.  Hence the 4017 reset pin sees 12V and the chip resets (and clears any illegal states).  Then the capacitor starts charging via the resistor so the 4017 reset pin soon sees a low-voltage on its reset pin causing the chip to exit the reset condition, and it starts counting based on the clock pulses from the 555.

 

The 555 has a so-called "active low" reset which means you briefly apply a low level (i.e., ground) signal to reset it. So in you schematic, this pin is connected "high" and the 555 is never in the reset condition.

 

Typically, in schematic drawings, you indicate an active-low pin by either designating the pin name with a bar over it or by inserting a small circle on the schematic symbol of that pin:

 

ogr 555 active low reset

Attachments

Images (1)
  • ogr 555 active low reset

OGR Publishing, Inc., 1310 Eastside Centre Ct, Suite 6, Mountain Home, AR 72653
800-980-OGRR (6477)
www.ogaugerr.com

×
×
×
×
×